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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10112/12437

タイトル: The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET
著者名: YOSHIOKA, Yoshimasa
HAMADA, Mitsuo
OMURA, Yasuhisa
著者の別表記: 吉岡, 由雅
大村, 泰久
キーワード: 関西大学
Kansai University
MOSFET
silicon-on-insulator
underlap gate
GIDL
analog
high-k insulator
論文発行年月日: 2008年3月20日
出版者: Kansai University
雑誌名: Science and Technology reports of Kansai University = 関西大学理工学研究報告
巻: 50
開始ページ: 17
終了ページ: 27
抄録: This paper describes the performance prospect of underlapped single-gate ultra-thin (USU) SOI MOSFET with a low-k or high-k gate dielectric from the viewpoint of both digital and analog applications. Increase in underlap length suppresses the threshold voltage variation as well as suppression of short-channel effects. In addition, the thickness of the SOI layer directly impacts the maximization of drive current (i. e., minimization of intrinsic delay time). Since the fringe capacitance is reduced in introduction of underlap region, effective gate capacitance is also reduced, while voltage gain of the device rises. Since apparent rise of cut-off frequency stems from the reduction of voltage gain, advancement of analog performance is inherentry limited. Use of a high-k gate dielectric basically reduces the gate-induced drain leakage (GIDL) current, while short-channel effects are degraded. In the case of very high dielectric constant, however, a very high electric-field region appearing far from the gate edge becomes a new source of high GIDL current. So, optimization of the dielectric constant of the gate insulator is required.
内容記述: ELECTRICAL AND ELECTRONIC ENGINEERING, 50th anniversary edition
資料種別: Departmental Bulletin Paper
URI: http://hdl.handle.net/10112/12437
ISSN: 04532198
書誌レコードID: AA12314657
著者版フラグ: publisher
出現コレクション:Science and Technology reports of Kansai University-No. 50

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